DFI UT X48-T3RS LanParty - Living Review

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Test Set Up & Initial Thoughts.

Here is the list of all the parts, in no particular order, backups/alternatives in red.

• CPU - Q6600 G0/E8500 Wolfdale/Q6600 G0 (replacement).
• RAM - Corsair PC3-12800 2x2GB Kit / Corsair PC3-12800 2x1GB kit / OCZ PC3-16000 2x1GB kit.
• Cooling - Thermalright Ultra 120 Extreme/LittleDevil's Single Stage Phase Unit.
• Graphics - 8800GT
• Hard Drive - Raptor 74GB 16MB
  
• PSU - Corsair HX620W

The system will be built up barebones on my bench - no case.

At this point, I would like to mention a few things that I consider noteworthy, such as the fact that the Thermalright Ultra Extreme (TRUE) heatsink will now fit vertically and allow the heat to be directed towards the rear exhaust fan of the case.

I'm pleased about this, it has been one of two constant gripes about the board layout, and here it is fixed.



Things are still tight, but it does fit properly now.



The other gripe about the layout on previous boards was that the top PCI-E slot was too close to the DRAM slots and this meant that you had to remove your graphics card to remove the RAM, which could be quite annoying if you had a watercooled graphics card.

This has now been addressed and the RAM can be removed quite easily, without the need to remove the graphics card.

While checking this out, it became more obvious that both 16x slots are very close together, in fact there is only a PCI slot to seperate them. I don't know of any cards that won't fit, but there could be an issue with ventilation on the upper most card if using a dual slot cooler. However, I suspect that most of us will be using a single card, and in that respect, the layout is much improved.

As you can see here, with the DRAM retention levers closed, there is enough room to open them.

Note: If, like me, you have sausage fingers, you can use a pen or a ruler to push the lower lever open .

Note 2: You can actually leave the lower lever closed and lift the RAM up in an upwards direction, and you can also refit the sticks in this manner as well.

Closed.



Open.





Next, the Genie BIOS...

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Initial Thoughts - Continued.

While I was fitting the TRUE, I decided to have a closer look at the removable part of the North Bridge heatsink. Below, you can see the clip on the NB heatsink, it's similar to the type of clip that you would find on old Socket A CPU heatsinks.

You can see the clip on the NB heatsink, it's a similar kind of clip that you would find on old Socket A CPU heatsinks.

Simply grab a small electrical screwdriver, gently push downwards and outwards and it will release - It is very easy and not a lot of pressure is
required - (Please be very careful when doing this as one slip could result in a gouged PCB!).



Once the heatsink is removed, we are left with a solid block of nickel plated copper which the heatpipes run through. The surface is very flat and shiney, and if you have ever seen the base of a Thermalright heatsink, it looks like that.

You can fit any suitable aftermarket heatsink here and you can also fit a suitable chipset waterblock if that's your thing. Personally, I think this is a fantastic idea.



The underside of the stock heatsink is flat, but not a mirror finish.



Next up, The Genie BIOS...

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The Genie BIOS.

As with all DFI boards, the sheer number of settings can be mind blowing when you first see them, but fortunately, the T3RS has been blessed with some very useable stock settings, so you can go at your own pace.

Genie BIOS Settings Main Page.



CPU Feature.

For overclocking purposes, it is best to disable all except the Core Multi Processing, although some people do like to use the power saving features when overclocked.



DRAM Timings Top Half.

This is where you tweak all those RAM timings, a full breakdown of all of them follows.



DRAM Timings Lower Half.

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The Genie BIOS - Part 2.

DRAM Timings In More Detail.

Clock Setting Fine Delay - Top Half.

Ch1 / Ch2 Clock Crossing Setting:
Auto / More aggressive /aggressive / Nominal / Relaxed / More Relaxed

"Giving an easy explanation, after the CPU, PCIE, DRAM locked the clock phase by “PLL phase locked loop”, we can utilize the DRAM DLL to adjust DRAM operating phase by tuning DRAM DATA output phase forward or backward to create a better match with current DATA operating phase.
The BIOS will automatically calculate a parameter after system boot up.
The BIOS will show the current value of this parameter.
The best tuning range for finding the best DATA operating phase will be 3 ranks before or after this current value."



Clock Setting Fine Delay - Lower Half.

Ch1Ch2 CommonClock Setting:
Auto / More aggressive /aggressive / Nominal / Relaxed / More Relaxed
"As above, it is PLL fine-tune for Common clock signals of DRAM modules"

Ch1/Ch2 RDCAS GNT-Chip Delay: Auto /1~7 CLK
"Read command rate, 1Clock is Intel Command rate 1N mode, 2~7Clock are 1N disable mode"

Ch1/Ch2 WRCAS GNT-Chip Delay: Auto /1~7 CLK
"Write command rate, 1Clock is Intel Command rate 1N mode, 2~7Clock are 1N disable mode"

Ch1/Ch2 Command to CS Delay: Auto /1~7 CLK
"DRAM module bank selecting command rate, 1Clock is Intel Command rate 1N mode, 2~7Clock are 1N disable mode"



Read Delay Phase Adjust.



Enhance Data Transmitting.



Enhance Addressing.



T2 Dispatch.



Continued below...

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The Genie BIOS - Part 3

DRAM Timings In More Detail - Continued.

CAS Latency Time (tCL).



RAS# to CAS# Delay (tRCD).



RAS# Precharge (tRP).



Precharge Delay (tRAS).



All Precharge to Act - Top Half.



All Precharge to Act - Lower Half.



Continued below...

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The Genie BIOS - Part 4

DRAM Timings In More Detail - Continued.

REF to ACT Delay (tRFC) - Top Half.



REF to ACT Delay (tRFC) - Lower Half.



Performance LVL (Read Delay) (Performance Level) - Top Half.

This is the tRD setting for your DRAM.



Performance LVL (Read Delay) (Performance Level) - Top Half.



MCH ODT Latency:

"DRAM ODT read/Write latency, (Basically ODT is On Die Termination, it likes a variable resistor termination to protect DATA signal integrity from high frequency interference)"



MCH ODT Latency - Lower Half.



Continued below...

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The Genie BIOS - Part 5

DRAM Timings In More Detail - Continued.

Write to PRE Delay (tWR) - Top Half.



Write to PRE Delay (tWR) - Lower Half.



Rank Write to Read (tWTR) - Top Half.



Rank Write to Read (tWTR) - Lower Half.



ACT to ACT Delay (tRRD) - Top Half.



ACT to ACT Delay (tRRD) - Lower Half.



Read To Write Delay (tRDWR) - Top Half.



Read To Write Delay (tRDWR) - Lower Half.



Continued below...

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The Genie BIOS - Part 6

DRAM Timings In More Detail - Continued.

Ranks Write to Write - Top Half (tWRWR).



Ranks Write to Write - Lower Half (tWRWR).



Ranks Read To Read (tRDRD) - Top Half.



Ranks Read To Read (tRDRD) - Lower Half.



Ranks Write To Read (tWRRD) - Top Half.



Ranks Write To Read (tWRRD) - Lower Half.



Continued below...

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The Genie BIOS - Part 7

DRAM Timings In More Detail - Continued.

Read CAS# Precharge (tRTP) - Top Half.



Read CAS# Precharge (tRTP) - Lower Half.



All PRE to Refresh - Top Half.



All PRE to Refresh - Lower Half.



CMD to CST Mode.



Continued below...

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The Genie BIOS - Part 8

The Voltage Settings.



The Voltage Settings In More Detail.

CPU VID Special Add: +100.23% - 130.00% - This will allow you to fine tune the CPU voltage. A calculator will be handy (unless you are good at maths ). All this does is add voltage in very fine increments. An example would be if you set 1.6v and you wanted 1.68v - you simply multiply the set vcore (1.6v) by the percentage value (104% in this case) and that gives you 1.68v. You don't have to use it for higher voltages either, and it can give you finer increments than the standard Vcore settings allow.

I noticed that the CPU VID Special wasn't available unless at least 1.2v CPU VID Control (Vcore) was set. I asked DFI why this was, and they explained that when less than 1.2v is selected for Vcore and VID Special is used, excessive ripple can be generated so, they decided to only allow the VID Special to be utilised after 1.2v.



CPU VID Special Add - Lower Half.



DRAM Voltage Control (1.208v - 2.45v) - Top Half.



DRAM Voltage Control (1.208v - 2.45v) - Lower Half.



SB Core / CPU PLL voltage: (1.51V-2.38V)

"These two voltages are controlling by same adjustable circuit, increasing CPU PLL voltage higher is better for gaining a stable OC situation." - Be careful with this! By raising this value, you can achieve stability at higher FSBs, but too high and you can degrade your CPU quite quickly, so if it's 24/7 settings you are looking for, try and keep this under 1.64v for 65nm CPUs. I didn't need to increase this to hit over 5Ghz on an E8500, so most people won't need to touch it, and also for 24/7 use, leave it alone.



NB Core Voltage (North Bridge Voltage) (1.265V-2.040V) - Top half.



NB Core Voltage (North Bridge Voltage) (1.265V-2.040V) - Lower Half.



Continued below...