DFI Lanparty DK X48-T2RSB - Living Review

[Shiranui Gen-An]

Clunk, any tips for the advanced driving strength options? I just got this board in yesterday and have been playing around with it a bit, but there doesn't seem to be much documentation about the different levels of data and clk strength and the DLL skews, i.e. does the strength increase as the numbers go up or decrease. There has to be some kind of logical methodology to selecting the values...

[Clunk]

Sorry for the late reply here, I completely missed your post

I don't have the board any longer and mine had a few options that didn't work as it was a pre-retail sample, but Praz is still working on his, so hopefully he can answer your question when he sees this

[Shiranui Gen-An]

I found an article on Madshrimps that explained what the options do that made sense to me. I figured out I first needed to find a skew model that will let me boot/fully post, then play with the drive strength options for memtest stability.

[Praz]

The DLL Skew models set signal timings between the Northbridge and memory modules and alter the impedance of the circuit to math the modules.

The two driving strengths seem to be grouped as two separate sets. Even numbers and odd numbers. The higher the number the stronger the signal.

Tuning DLL model first is the best course of action. Because of impedance and signal swing the optimal settings can change based of the FSB.

[Praz]

DFI DK X48-T2RSB PLUS, 09/23 BIOS
550x8, Memory 1100MHz
E8600
2x2GB OCZ Flex II PC2-9200 1150MHz 5-5-5-18
SAPPHIRE 4870 Crossfired
Orange Slots Used For Memory

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CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O.C. Fail Retry Counter...................0
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio...........................8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................550 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................200ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................400/800
PCIE Clock................................105MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................Auto
CPU VID Special Add.......................115%
DRAM Voltage Control......................2.000V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.604V
CPU VTT Voltage...........................1.415V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
MCH RON Offset Value......................00
MCH RTT Offset Value......................00
MCH Slew Rate Offset Value................00
MCH VREF 1 Value..........................A8
MCH VREF 2 Value..........................B0
MCH VREF 3 Value..........................A8
CPU GTL 0/2 REF Volt......................0.667X
CPU GTL 1/3 REF Volt......................0.667X
North Bridge GTL REF Volt ................0.61X

DRAM Timing Page
Enhance Data Transmitting.................Auto
Enhance Addressing........................Auto
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below

CAS Latency Time (tCL)....................Auto
RAS# to CAS# Delay (tRCD).................Auto
RAS# Precharge (tRP)......................Auto
Precharge Delay (tRAS)....................Auto
All Precharge to Act......................Auto
REF to ACT Delay (tRFC)...................Auto
Performance Level.........................Auto
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DRAM CLK Driving Strength.................Level 2
DRAM Data Driving Strength................Level 6
Ch1 DLL Default Skew Model................Model 0
Ch2 DLL Default Skew Model................Model 0

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 1862ps
DIMM 2 Clock fine delay...................Current  979ps
DIMM 1 Control fine delay.................Current 1046ps
DIMM 2 Control fine delay.................Current  445ps
Ch 1 Command fine delay...................Current   56ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 1862ps
DIMM 4 Clock fine delay...................Current  912ps
DIMM 3 Control fine delay.................Current  890ps
DIMM 4 Control fine delay.................Current  879ps
Ch 2 Command fine delay...................Current   56ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

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[Praz]

XP SP3


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3dx Max 2009 w/V-ray
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1GB VOB file ripped from DVD movie

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[Praz]

Vista 64 Bit SP1


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3dx Max 2009 w/V-ray
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TMPGEnc XPress
1GB VOB file ripped from DVD movie

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[Kelainefes]

WOW those are some mean VTT and NB voltages right there!
Anyway excellent results.

[Praz]

The voltages are at the minimum needed for stability. I think I've got the same FSB posted in this thread for 2x1GB of ram. Didn't need anywhere near these voltages. This run also required the MCH VREF settings to be manually set.

[Shiranui Gen-An]

I'm amazed at your Cellshock 8000 C4 600MHz settings, Praz. I have that same kit, and I can get mine stable at DDR2-1200 with 2.05V on the 5:6 divider, but not with any of the clock crossing settings set to "More Aggressive." Mine also needed a different skew model.