DFI Lanparty DK X48-T2RSB - Living Review - Page 5

eva2000 · #41 27-10-2008, 05:03

Quote:

Originally Posted by Praz

I think you'll like it. The board clocks so easy at times I forgot I was working with a DFI. VTT seems to be the key with this board. Using a dual core CPU the NB is the determining factor for the amount of VTT based on the type of ram being used.

Been playing with my DK X48-T2RBS Plus and fsb wise it's much better than previous DFI boards I have played with P35/X38/X48 which got stuck around 500-510FSB 32M Pi, while this board manages 563FSB 32M Pi DFI Lanparty DK X48-T2RBS Plus bios, info, photos & overclocking tips

Max validation @571FSB so far:

Memory clocking ain't half bad either

tRD/Performance level = 7

2x1GB Teamgroup PC2-10400 CAS6 @701Mhz 5-5-5-18 at 2.675v

2x1GB Crucial Ballistix PC2-8500 Tracer Micron D9GMH @698Mhz 5-5-5-18 at 2.65v for CPUZ Validation

Teamgroup PC2-10400

Crucial Ballistix PC2-8500 Tracer

Clunk · #42 27-10-2008, 05:21

Great job mate

eva2000 · #43 27-10-2008, 17:16

Thanks, I'm loving this board!

Max 32M Pi & Max CPUZ Validation
on H20

Time to push the E8600 Q820A599 *0464 cpu and Crucial Ballistix PC2-8500 Tracer memory and they certainly didn't disappoint - max highest H20 cooled Super Pi 32M yet @5093Mhz! To think this E8600 Q820A599 *0464 only did max Super Pi 1M @4952Mhz and max validation @5079Mhz at 1.552v idle on Gigabyte EP45-Extreme with exact same cooling setup.

Even better than my E8600 Q820A599 *0537 which did Super Pi 32M @5003Mhz at 1.568v idle with max CPUZ Validation @5146Mhz on DFI UT X48-T3RS DDR3 board.

E8600 Q820A599 *0464

Max CPUZ Validation @5146Mhz at 1.600v idle / 1.568v load
Super Pi 32M @5093Mhz at 1.600v idle / 1.568v load
Super Pi 32M @5025Mhz at 1.552v idle / 1.520v load

@5146Mhz

@5093Mhz - click image for full screenshot

@5025Mhz - click image for full screenshot

System:

E8600 Q820A599 0464
CPU Cooling: Dtek Fuzion Rad Tower Box
DFI LP DK X48-T2RBS Plus - 9/23 beta bios
128MB Gainward FX5200 PCI
2x1GB Crucial Ballistix PC2-8500 Tracer double sided Micron D9GMH dual channel kit
Memory cooling: 120x25mm Thermaltake 81cfm fan
750GB Samsung SATAII
Pioneer 215 DVD-RW
1200W Silverstone OP1200
WinXP Pro SP2 Nlite Fully Updated.

Praz · #44 28-10-2008, 19:32

DFI DK X48-T2RSB PLUS, 09/23 BIOS
475x9.5, Memory 1140MHz
E8600
2x2GB OCZ Flex II PC2-9200 1150MHz 5-5-5-18
SAPPHIRE 4870
Yellow Slots Used For Memory

click for larger image

click for larger image

Code:

CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
O.C. Fail Retry Counter...................0
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio...........................9.5x
CPU N/2 Ratio.............................Enabled
CPU Clock.................................475 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................0ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................333/800
PCIE Clock................................100MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................1.41875
CPU VID Special Add.......................Auto
DRAM Voltage Control......................2.000V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.555V
CPU VTT Voltage...........................1.160V
VCore Droop Control.......................Disabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
MCH RON Offset Value......................00
MCH RTT Offset Value......................00
MCH Slew Rate Offset Value................00
MCH VREF 1 Value..........................00
MCH VREF 2 Value..........................00
MCH VREF 3 Value..........................80
CPU GTL 0/2 REF Volt......................0.648X
CPU GTL 1/3 REF Volt......................0.667X
North Bridge GTL REF Volt ................0.67X

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Enabled
Clock Setting Fine Delay..................Listed Below

CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................18
All Precharge to Act......................6
REF to ACT Delay (tRFC)...................54
Performance Level.........................7
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................14
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................Auto

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DRAM CLK Driving Strength.................Level 2
DRAM Data Driving Strength................Level 6
Ch1 DLL Default Skew Model................Model 0
Ch2 DLL Default Skew Model................Model 0

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current 1840ps
DIMM 2 Clock fine delay...................Current  957ps
DIMM 1 Control fine delay.................Current 1023ps
DIMM 2 Control fine delay.................Current  434ps
Ch 1 Command fine delay...................Current  33ps

Ch2 Clock Crossing Setting................More Aggressive
DIMM 3 Clock fine delay...................Current 1840ps
DIMM 4 Clock fine delay...................Current  890ps
DIMM 3 Control fine delay.................Current  868ps
DIMM 4 Control fine delay.................Current  857ps
Ch 2 Command fine delay...................Current  33ps

Ch1Ch2 CommonClock Setting................More Aggressive

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto