DFI Lanparty DK X48-T2RSB - Living Review - Page 4

Praz · #31 17-09-2008, 18:36

Vista 64 Bit SP1

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Praz · #32 17-09-2008, 21:46

DFI DK X48-T2RSB PLUS, 08/29 BIOS
550x8, Memory 1110MHz
E8600
2x1GB Cell Shock PC2-8000 1000MHz 4-4-4-12
SAPPHIRE 4870
Orange Slots Used For Memory

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Code:

CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O.C. Fail Retry Counter...................0
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio...........................8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................550 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................200ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................333/667
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................Auto
CPU VID Special Add.......................111%
DRAM Voltage Control......................2.000V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.543V
CPU VTT Voltage...........................1.210V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
MCH RON Offset Value......................00
MCH RTT Offset Value......................00
MCH Slew Rate Offset Value................00
MCH VREF 1 Value..........................00
MCH VREF 2 Value..........................00
MCH VREF 3 Value..........................00
CPU GTL 0/2 REF Volt......................0.667X
CPU GTL 1/3 REF Volt......................0.667X
North Bridge GTL REF Volt ................0.61X

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Enabled
Clock Setting Fine Delay..................Listed Below

CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................Auto
REF to ACT Delay (tRFC)...................Auto
Performance Level.........................Auto
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DRAM CLK Driving Strength.................Level 6
DRAM Data Driving Strength................Level 8
Ch1 DLL Default Skew Model................Model 5
Ch2 DLL Default Skew Model................Model 5

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 1886ps
DIMM 2 Clock fine delay...................Current 1012ps
DIMM 1 Control fine delay.................Current 962ps
DIMM 2 Control fine delay.................Current 962ps
Ch 1 Command fine delay...................Current 1412ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 1737ps
DIMM 4 Clock fine delay...................Current 800ps
DIMM 3 Control fine delay.................Current 724ps
DIMM 4 Control fine delay.................Current 86ps
Ch 2 Command fine delay...................Current 1486ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

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Praz · #33 17-09-2008, 21:47

XP SP3

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Praz · #34 17-09-2008, 21:47

Vista 64 Bit SP1

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Clunk · #35 17-09-2008, 22:29

Nice work John as always

Praz · #36 18-09-2008, 15:00

Thanks Dave. These runs were pretty much plug n' play. It's one sweet board and that's a refreshing change.

eva2000 · #37 18-09-2008, 17:23

wow love the FSB you managed.. highest i've seen for a DFI x48 board in ages!

should be setting up my DK X48-T2RSB Plus this weekend hopefully FSB is up there with yours

Praz · #38 18-09-2008, 18:10

Quote:

Originally Posted by eva2000

wow love the FSB you managed.. highest i've seen for a DFI x48 board in ages!

should be setting up my DK X48-T2RSB Plus this weekend hopefully FSB is up there with yours

I think you'll like it. The board clocks so easy at times I forgot I was working with a DFI. VTT seems to be the key with this board. Using a dual core CPU the NB is the determining factor for the amount of VTT based on the type of ram being used.