DFI UT X48-T3RS LanParty - Living Review - Page 58

Praz · #**571** 02-11-2008, 04:11

DFI LP UT X48-T3R, 09/23 BIOS
540x8, Memory 1800MHz
E8600
2x1GB OCZ nVidia SLI PC3-16000 2000MHz 9-9-9-30
SAPPHIRE 4870
Yellow Slots Used For Memory

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Code:

CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown after AC loss....................Disabled
O.C. Fail Retry Counter...................0
CPU Clock Ratio........................... 8 X
CPU N/2 Ratio.............................Disabled
CPU Clock.................................540 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................900mV
CPU Clock0 Skew...........................200ps
CPU Clock0 Skew...........................  0ps
DRAM Speed................................400/1333
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

Voltage Setting Page 
CPU VID Control...........................1.3125V
CPU VID Special Add Limit.................Enabled
CPU VID Special Add.......................Auto
DRAM Voltage Control......................1.903V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.630V
CPU VTT Voltage...........................1.330V
VCore Droop Control.......................Disabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Strong
MCH RON Offset Value......................00
MCH RTT Offset Value......................00
MCH Slew Rate Offset Value................00
MCH VREF 1 Value..........................00
MCH VREF 2 Value..........................00
MCH VREF 3 Value..........................80
GTL REF Voltage Control...................Enabled
CPU GTL 1/2 REF Volt...................... 88
CPU GTL 1/3 REF Volt...................... 88
North Bridge GTL REF Volt ................ 45

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................Listed Below

CAS Latency Time (tCL)....................8
RAS# to CAS# Delay (tRCD).................8
RAS# Precharge (tRP)......................8
Precharge Delay (tRAS)....................24
All Precharge to Act......................9
REF to ACT Delay (tRFC)...................60
Performance Level.........................9
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................18
Rank Write to Read (tWTR).................19
ACT to ACT Delay (tRRD)...................10
Read to Write Delay (tRDWR)...............9
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................5
ALL PRE to Refresh........................9

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DRAM CLK Driving Strength.................Level 5
DRAM Data Driving Strength................Level 8
Ch1 DLL Default Skew Model................Model 0
Ch2 DLL Default Skew Model................Model 0

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current  489ps
DIMM 2 Clock fine delay...................Current  489ps
DIMM 1 Control fine delay.................Current  434ps
DIMM 2 Control fine delay.................Current  473ps
Ch 1 Command fine delay...................Current  182ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current  686ps
DIMM 4 Clock fine delay...................Current  686ps
DIMM 3 Control fine delay.................Current  607ps
DIMM 4 Control fine delay.................Current  654ps
Ch 2 Command fine delay...................Current  371ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

Common CMD to CS Timing...................  1N

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Praz · #**572** 02-11-2008, 04:12

XP SP3

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3dx Max w/V-ray
Time to render: 13min 03sec

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Praz · #**573** 02-11-2008, 04:13

Vista 64 Bit SP1

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3dx Max w/V-ray
Time to render: 14min 08sec

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BlackDragon24 · #**574** 03-11-2008, 17:51

E8600 8 x 540 @ 1.344 - 1.360v under load. This was a first run and I'm still in a process of dialing down voltages.

I think I must've deleted my original pic with orthos 8h stable and memtest bandwidth....here;s a replacement for now but only 2.5 hours orthos stable before I had to stop it so the wife could use the puter

:

Its also stable for a 2h run of Far Cry 2 with everything on ultra high and 8X AA

BlackDragon24 · #**575** 04-11-2008, 05:21

I tell ya, DFI needs to figure out who pays the bills.

Praz · #**576** 04-11-2008, 05:27

Quote:

Originally Posted by BlackDragon24

I tell ya, DFI needs to figure out who pays the bills.

I contacted someone in Taiwan a couple of hours ago but it was only 2:30am there so it will be a bit before things are sorted.

Clunk · #**577** 04-11-2008, 05:34

What's happened?

Praz · #**578** 04-11-2008, 05:40

Not sure what really happens. The page displayed is a billing notice but it is a default 404 page not a real billing issue. The server needs to be reset and it only happens to the server for the U.S forum.

Clunk · #**579** 04-11-2008, 05:50

Strange.

mrt181 · #**580** 04-11-2008, 21:12

Hi, Clunk thank you for this great review and site. I was recently infected with the desire to OC. i have read your DFI BIOS guide and your C2D OC guide.

I tried to overclock to a moderate 3.4GHz, FSB 400MHz and RAM 1600MHz. I have increased the CPU voltage to 1.35V and the RAM voltage to 1.855, my RAM timings are 7-7-7-20 (they are rated 7-7-6-18@1600MHz). I saved this settings as described in your guide. Everytime i try to boot i get a checksum error and the default settings are loaded.

What have i done wrong? If you do not bother with noobs, could you point me to another site for help.