Got a new E8400 Q829A234 Testing right now.
By using E8600 Q820A628 I am using this setting for 7/24
CPU Feature Page
Thermal Management Control...........Disabled
PPM (EIST) Mode...........................Disabled
Limit CPUID MaxVal.........................Disabled
CIE Function.................................Disabled
Virtualization Technology.................Disabled
Core Multi-Processing......................Enabled
Main
BIOS Page
Exist Setup Shutdown......................Mode 1
Shutdown After AC Loss...................Disabled
O. C. Fail Retry Counter...................3
CLOCK VC0 Divider..........................Auto <- I don't have this setting?
CPU Clock Ratio..............................8x
CPU N/2 Ratio................................Disabled
CPU Clock.....................................535 MHz
Boot Up Clock................................Auto
CPU Clock Amplitude.......................900mV
CPU Clock0 Skew...........................500ps
CPU Clock1 Skew............................200ps
DRAM Speed..................................400/1333
PCIE Clock....................................105MHz
PCIE Slot Config.............................1X 1X
CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum.....................Disabled <- I don't have this setting?
Voltage Setting Page
CPU
VID Control...............................1.318750v
CPU
VID Special Add Limit..................Disabled
CPU
VID Special Add.........................101.xx% <- FORGOT
DRAM Voltage Control.......................2.08V
SB Core/CPU
PLL Voltage...................1.640V
NB Core Voltage...............................1.591V
CPU
VTT Voltage..............................1.29V
VCore Droop Control..........................Disabled
Clockgen Voltage Control...................3.60V
GTL+ Buffers Strength.......................Strong
Host Slew Rate................................Weak
GTL REF Voltage Control....................Enabled
MCH vREF 1.....................................30
MCH vREF 2.....................................30
MCH vREF 3.....................................B0
CPU
GTL 1/2
REF Volt........................93
CPU
GTL 0/3
REF Volt........................90
North Bridge
GTL REF Volt ..................55
DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing..........................Fast
T2 Dispatch....................................Disabl ed
Clock Setting Fine Delay....................Listed Below
CAS Latency Time (tCL)....................6
RAS# to CAS# Delay (tRCD)...............6
RAS# Precharge (tRP).......................5
Precharge Delay (tRAS).....................16
All Precharge to Act.........................Auto
REF to ACT Delay (tRFC)...................48
Performance Level............................8
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency............................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR)................Auto
ACT to ACT Delay (tRRD)...................2
Read to Write Delay (tRDWR)..............Auto
Ranks Write to Write (tWRWR)............Auto
Ranks Read to Read (tRDRD)...............Auto
Ranks Write to Read (tWRRD)..............Auto
Read CAS# Precharge (tRTP)..............5
ALL PRE to Refresh............................Auto
Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto
Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto
Clock Setting Fine Delay Page
DRAM Clk Driving Strength...................Level 5
DRAM Data Driving Strength.................Level 8
Ch1 DLL Default Skew Model................Model 1
Ch2 DLL Default Skew Model................Model 1
Fine Delay Step Degree....................5ps
Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current
DIMM 2 Clock fine delay...................Current
DIMM 1 Control fine delay.................Current
DIMM 2 Control fine delay.................Current
Ch 1 Command fine delay..................Current
Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current
DIMM 4 Clock fine delay...................Current
DIMM 3 Control fine delay.................Current
DIMM 4 Control fine delay.................Current
Ch 2 Command fine delay..................Current
Ch1Ch2 CommonClock Setting............More Aggressive
Ch1 RDCAS GNT-Chip Delay...............Auto
Ch1 WRCAS GNT-Chip Delay..............Auto
Ch1 Command to CS Delay................Auto
Ch2 RDCAS GNT-Chip Delay...............Auto
Ch2 WRCAS GNT-Chip Delay..............Auto
Ch2 Command to CS Delay................Auto
Common CMD to CS Timing................1N
Linear Mode
