DFI UT X48-T3RS LanParty - Living Review - Page 17

Clunk · #**161** 23-06-2008, 03:36

For 445FSB, you can go for either. It really does come down to money at the end of the day.

Also, if you go for the T3RS, get wherever you buy it from to flash it to 0609 before they send it, that way, you can pretty much buy any DDR3 memory you like.

Clunk · #**162** 23-06-2008, 05:35

Quick Update:

Spoke to DFI tonight and they said that they had managed 500FSB easily enough with the 420 BIOS.

This is puzzling because Supershanks also has the T3RS and also has the same OCZ kit as me and he has been stuck around the same FSB 480-490. Anyway, it turns out that the OCZ sticks use Samsung IC's and they like a tRFC of 100+.

The problem is that the T3RS only goes up to 77, so this is where the instability is probably happening.

They have a BIOS on the way that will allow a tRFC of 120 (ish) and hopefully that will fix the issue.

We also have another beta BIOS that fixes a few minor memory issues, so I have attatched it here.

Use the Beta BIOS at your own risk.

Praz · #**163** 23-06-2008, 13:29

Still need to run game benchmarks. Then I'll post the rest of the screenshots.

click for larger image

Clunk · #**164** 23-06-2008, 14:43

Nice going Praz

Are you able to do 500/2000?

Praz · #**165** 23-06-2008, 15:00

Quote:

Originally Posted by Clunk

Are you able to do 500/2000?

Haven't had any 1GB sticks in the board yet. It may be a bit. I'm anxious to see what the board does with 4x2GB. Something I found with the 1600EB 2x2GB stick is they will not run at 1N. But as the other screenshots will show, performance doesn't seem to suffer at 2N.

Fiery has been working on Everest so it properly supports this board. The latest version he sent now identifies the board but some sensor info is still missing. Will post a link when it's done.

Clunk · #**166** 23-06-2008, 15:24

Thanks

Praz · #**167** 24-06-2008, 01:10

DFI LP UT X48-T3RS, 06/09 BIOS
E8400
500x8, Memory 1666MHz
2x2GB OCZ PC3-12800 1600MHz Platinum EB
XFX8800 GTS (G92)
tRD - 8.5, Memset Misreads The Value When Set Manually
Memory Speed - 1666MHZ, CPU-Z Misreports The Divider
Yellow Slots Used For Memory

click for larger image

click for larger image

Code:

CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Disabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Disabled
Virtualization Technology.................Disabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O. C. Fail Retry Counter..................0
CLOCK VC0 Divider.........................Auto
CPU Clock Ratio...........................8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................500 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................0ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................400/1333
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................1.31255V
CPU VID Special Add Limit.................Enabled
CPU VID Special Add.......................Auto
DRAM Voltage Control......................1.855V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.630V
CPU VTT Voltage...........................1.325V
VCore Droop Control.......................Disabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Strong
GTL REF Voltage Control...................Disabled
CPU GTL 1/2 REF Volt......................113
CPU GTL 0/3 REF Volt......................100
North Bridge GTL REF Volt ................100

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................7
RAS# to CAS# Delay (tRCD).................6
RAS# Precharge (tRP)......................6
Precharge Delay (tRAS)....................20
All Precharge to Act......................Auto
REF to ACT Delay (tRFC)...................Auto
Performance Level.........................9
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Enabled
Channel 1 Phase 1 Pull-In.................Enabled
Channel 1 Phase 2 Pull-In.................Enabled
Channel 1 Phase 3 Pull-In.................Enabled
Channel 1 Phase 4 Pull-In.................Enabled

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DRAM Default Skew Model...................Model 3

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 489ps
DIMM 2 Clock fine delay...................Current 489ps
DIMM 1 Control fine delay.................Current 434ps
DIMM 2 Control fine delay.................Current 473ps
Ch 1 Command fine delay...................Current 560ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 686ps
DIMM 4 Clock fine delay...................Current 686ps
DIMM 3 Control fine delay.................Current 607ps
DIMM 4 Control fine delay.................Current 654ps
Ch 2 Command fine delay...................Current 639ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

Common CMD to CS Timing...................2N