DFI UT P45-T3RS Living Review

[supershanks]

Bios - 2 of 4
Advanced Chipset Features


Integrated Peripherals
[b][u]
OnChip IDE Device
Option 1- Green (Intel Sata to you & me )

Option 2 - IDE + Yellow Jmicron Sata Slots

Onboard Devices

Siper I/O

USB

[supershanks]

Bios 3 of 4
Power Management Setup

PCI/PNP

PC Health
Top

Bottom

[supershanks]

Genie Bios 1 of 2
Top of main Genie Bios Page


CPU Feature Sub Menu


Dram Timings Sub Menu

Voltage Settings Sub Menu

Exit Setup shutdown

OC Fail Retry Counter

OC Fail Cmos Reloaded

CPU Multi

CPU N/2 Ratio - Enable CPU half multi for 45nm CPUs

CPU Clock FSB

CPU Clock Amplitude

[supershanks]

Genie Bios 2 of 2

Bottom of main Genie Bios Page


CPU Clock Skew


Dram Speed


PCI-E Clock

PCI-E Configuration

CPU Spread Spectrum

PCI-E Spread Spectrum

[supershanks]

Genie Bios - Dram Timing Sub Menu
Top of Dram Timing Page


Enhance Data Transmitting
[b][u]
Enhance Addressing

T2 Despatch


Clock Settings Sub Menu
Top

Bottom


Flex Memory Mode


Common CMD to CS Timing


Read Delay Phase Adjust - Sub Menu

Bottom of Dram Timing Page

[supershanks]

Genie Bios - Voltage Settings - Sub Menu (1of2)
Top

Bottom


CPU Vid Control
Low

High


CPU Vid Special Add
Low

High


Dram Voltage Control
Low

High


SB Core/CPU PLL Voltage


Continued in next post :-

[supershanks]

Genie Bios - Voltage Settings - Sub Menu (2of2)

NB Core Voltage
Low

High


CPU VTT Voltage
Low

High


Vcore Droop Control


Clockgen Voltage


GTL+ Buffer Strength


CPU GTL 0~3 Ref Voltage
Low

High

NB GTL 0~1 Ref Voltage
Low

High

FSB Vref
Low

High

[supershanks]

Bios 4 of 4
Cmos Reloaded keep those killer settings
Top

Bottom

[supershanks]

Build observations
Build went smoothly, as always it 's a point where you gain a valuable impression of the board

There are a couple of design areas which are or may be issues for some:-
1) Northbridge heatsink. The height of the heatsink means that you won't be able to mount a tower air cooler such as the Thermalright True 120 laterally so it blows through the rear case fan.
2) A graphics card using PCI-E slot 1. is very tight on the memory slots. This isn't unusual on a 775 board , but in this case changing ram means removing the graphics card. Using the central PCI-E slot isn'tt an option most will want to take as that slot is restricted to x8 rather than x16 bandwidth.


Good points
The addition of the Smart Connectors makes things a lot easier. I have a fan controller that has a usb interface, for compatibility it has single pin connections. It's always a pain connecting it to the usb header on a motherboard. Not any more

Similarly connecting the case connections to the front panel is now a doddle:-
Target area

Just fit the leads to the connection.

Than clip the smart connect in place.


Sound Card
I've always liked the design and elegance of the soundcard and it's connector

Fitted with front panel sound lead connected.

[supershanks]

PHP Code:

[code]
[b][u]DFI UT P45-T3RS LanParty[/u][/b][u][/u]
[b]CPU Feature - Sub Menu[/b]
Thermal Management Control.......: Enabled
PPM(EIST) Mode...................: Disabled
Limit CPUID MaxVal...............: Disabled
CIE Function.....................: Disabled
Execute Disable Bit..............: Disabled
Virtualization Technology........: Disabled
Core Multi-Processing............: Enabled
--------End Sub Menu--------
[b]Dram Timing - Sub menu[/b]
Enhance Data transmitting........: Auto
Enhance Addressing...............: Auto
T2 Dispatch......................: Auto

[b]Clock Setting Fine Delay - Sub Menu[/b]
DLL and RCOMP Settings...........: Auto
CH1 Dram Default Skew............: Model0
CH2 Dram Default Skew............: Model0
RCOMP Setting....................: Model0
Fine Delay Step Degree...........: 70ps
Ch1 Clock Crossing Setting.......: Auto
DIMM 1 Clock fine delay..........: Current 150ps
DIMM 2 Clock fine delay..........: Current 281ps
Ch1 Control0 fine delay..........: Current 170ps
Ch1 Control1 fine delay..........: Current 170ps
Ch1 Control0 fine delay..........: Current 170ps
Ch1 Control2 fine delay..........: Current 307ps
Ch1 Control3 fine delay..........: Current 307ps
Ch1 Command fine delay...........: Current 240ps
Ch2 Clock Crossing Setting.......: Auto
DIMM 3 Clock fine delay..........: Current 150ps
DIMM 4 Clock fine delay..........: Current 281ps
Ch2 Control0 fine delay..........: Current 170ps
Ch2 Control1 fine delay..........: Current 170ps
Ch2 Control0 fine delay..........: Current 170ps
Ch2 Control2 fine delay..........: Current 307ps
Ch2 Control3 fine delay..........: Current 307ps
Ch2 Command fine delay...........: Current 240ps

CH1Ch2 CommonClock Setting.......: Auto
Ch1 RDCAS GNT-Chip Delay.........: Auto
Ch1 WRCAS GNT-Chip Delay.........: Auto
Ch1 Command to CS Delay..........: Auto

Ch2 RDCAS GNT-Chip Delay.........: Auto
Ch2 WRCAS GNT-Chip Delay.........: Auto
Ch2 Command to CS Delay..........: Auto 
--------End Clock Setting Fine Delay Sub Menu--------

Flex Memory Mode.................: Auto
CAS Latency Time (tCL)...........: 
RAS# to CAS# Delay (tRCD)........: 
RAS# Precharge (tRP).............: 
Precharge Delay (tRAS)...........:
All Precharge to Act.............:
REF to ACT Delay (tRFC)..........:
Performance LVL (Read Delay).....: 

[b]Read delay phase adjust - Sub Menu[/b]
Ch1 Read delay phase (4~0)
Channel 1 Phase 0 Pull-In........: Auto
Channel 1 Phase 1 Pull-In........: Auto
Channel 1 Phase 2 Pull-In........: Auto
Channel 1 Phase 3 Pull-In........: Auto
Channel 1 Phase 4 Pull-In........: Auto
Ch2 Read delay phase (4~0)
Channel 2 Phase 0 Pull-In........: Auto
Channel 2 Phase 1 Pull-In........: Auto
Channel 2 Phase 2 Pull-In........: Auto
Channel 2 Phase 3 Pull-In........: Auto
Channel 2 Phase 4 Pull-In........: Auto
--------End Read Delay Sub Menu--------

Write to PRE Delay (tWR).........: Auto
Rank Write to Read (tWTR)........: Auto
ACT to ACT Delay (tRRD)..........: Auto
Read to Write Delay (tRDWR)......: Auto
Ranks Write to Write (tWRWR).....: Auto
Ranks Read to Read (tRDRD).......: Auto
Ranks Write to Read (tWRRD)......: Auto
Read CAS# Precharge (tRTP).......: Auto
ALL PRE to Refresh: Auto 
--------End Dram Timing Sub Menu--------

[b]Voltage Setting - Sub Menu[/b]
CPU VID Control..................: v 
CPU VID Special Add Limit........: Enabled
CPU VID Special Add..............: Auto
DRAM Voltage Control.............: V
SB Core/CPU PLL Voltage..........: V
NB Core Voltage..................: V
CPU VTT Voltage..................: V
Vcore Droop Control..............: Enabled
Clockgen Voltage Control.........: 3.45v
GTL+ Buffers Strength............: Strong
CPU GTL 0 REF Volt...............: 
CPU GTL 2 REF Volt...............: 
CPU GTL 1 REF Volt...............: 
CPU GTL 3 REF Volt...............: 
NB GTL 0 REF Volt................: 
NB GTL 1 REF Volt................: 
FSB Vref.........................:
--------End Voltage Sub Menu--------


Exist Setup Shutdown: Mode 2
Shutdown after AC Loss...........: Enabled
AC Shutdown Free.................: Enabled
O.C. Fail retry Counter..........: 1
O.C Fail Cmos Reload.............: Disabled
CPU Clock Ratio..................:
CPU N/2 ratio....................: Enanbled Disabled
Target CPU Clock.................: MHz
CPU Clock........................: MHz
Boot Up Clock....................: Auto
CPU Clock Amplitude..............: mV
CPU Clock0 Skew..................: 0ps
CPU Clock1 Skew..................: 0ps
DRAM Speed.......................: 
Target DRAM Speed................: MHz
PCIE Clock.......................: MHz
PCIE Slot Config.................: 
CPU Spread Spectrum..............: Disabled
PCIE Spread Spectrum.............: Disabled

[/code]