Genie
BIOS Template.
[code]
CPU Feature
Thermal Management Control: Disabled
PPM(EIST) Mode: Disabled
Limit CPUID MaxVal: Disabled
CIE Function: Disabled
Execute Disable Bit: Disabled
Virtualization Technology: Disabled
Core Multi-Processing: Enabled
Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio: 7.5x
Target CPU Clock: 3000MHz
CPU Clock:400
Boot Up Clock:Auto
DRAM Speed:400/1066
Target DRAM Speed:1066
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
Voltage Settings
CPU
VID Control:auto 1.2325
CPU
VID Special Add:auto
DRAM Voltage Control:2.1
SB Core/CPU
PLL Voltage:1.510
NB Core Voltage:1.278
CPU
VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3
REF Volt: 110
x CPU
GTL 0/2
REF Volt: 110
x North Bridge
GTL REF Volt: 110
DRAM Timing
Enhance Data transmitting: AUTO
Enhance Addressing: AUTO
T2 Dispatch: Disabled
Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
DIMM 1 Clock fine delay: Current
DIMM 2 Clock fine delay: Current
Ch 1 Command fine delay: Current
Ch 1 Control fine delay: Current
Ch2 Clock Crossing Setting: AUTO
DIMM 3 Clock fine delay: Current
DIMM 4 Clock fine delay: Current
Ch 2 Command fine delay: Current
Ch 2 Control fine delay: Current
Ch1Ch2 CommonClock Setting: Auto
Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto
Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto
CAS Latency Time (tCL):5
RAS# to CAS# Delay (tRCD):5
RAS# Precharge (tRP):5
Precharge Delay (tRAS):15
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO
Read delay phase adjust: Enter
Ch1 Read delay phase (4~0)
Channel 1 Phase 0 Pull-In: Auto
Channel 1 Phase 1 Pull-In: Auto
Channel 1 Phase 2 Pull-In: Auto
Channel 1 Phase 3 Pull-In: Auto
Channel 1 Phase 4 Pull-In: Auto
Ch2 Read delay phase (4~0)
Channel 2 Phase 0 Pull-In: Auto
Channel 2 Phase 1 Pull-In: Auto
Channel 2 Phase 2 Pull-In: Auto
Channel 2 Phase 3 Pull-In: Auto
Channel 2 Phase 4 Pull-In: Auto
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO
Thanks clunk, have read, saved, reread, the stickies, need some base figures for something similar and the GTLref stuff is a bit unnerving for a noobie, so trying to avoid that.
Feels like it's slower and a lot more unstable at 5-5-5-18 than at 5-5-5-15, also rasing dram volt to 2.19v kills the stab, even with a higher
NB v(+-1.31v)