Hi Clunk and thanks for the response.
I updated my
Bios about 4-5 weeks ago when i got the board, but i will see if there is a new
bios for it asap. Problem is i get on the DFI site but i can't select things or see anything there. Haven't found out whats blocking it. Maybe something from the router as i get the same prob on another PC. Anyway i get on that this evening with a friend who can get on their site.
Cooling is good i think. Got 3 Fan's. One from the front and one from the side and one blowing out at the back.
Here the
BIOS Template:
Genie
BIOS Template
DFI UT X48 LanParty
CPU Feature
Thermal Management Control: Disabled
PPM(EIST) Mode: Disabled
Limit CPUID MaxVal: Disabled
CIE Function: Disabled
Execute Disable Bit: Disabled
Virtualization Technology: Disabled
Core Multi-Processing: Enabled
Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter: 0
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 6X
Target CPU Clock: 1998 MHz
CPU Clock: 333 MHz
Boot Up Clock: AUTO
DRAM Speed: AUTO
Target DRAM Speed: DDR2 800
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
Voltage Settings
CPU
VID Control: AUTO 1.2325v
CPU
VID Special Add: AUTO
DRAM Voltage Control: 1.904v
SB Core/CPU
PLL Voltage: 1.510v
NB Core Voltage: 1.265v
CPU
VTT Voltage: 1.100v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3
REF Volt: 110
x CPU
GTL 0/2
REF Volt: 110
x North Bridge
GTL REF Volt: 110
CPU Core Voltage 1.16v
DRAM Voltage 1.88v
NB Core Voltage 1.29v
CPU
VTT Voltage 1.12v
DRAM Timing
Enhance Data transmitting: AUTO
Enhance Addressing: AUTO
T2 Dispatch: Disabled
Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
DIMM 1 Clock fine delay: Current
DIMM 2 Clock fine delay: Current
Ch 1 Command fine delay: Current
Ch 1 Control fine delay: Current
Ch2 Clock Crossing Setting: AUTO
DIMM 3 Clock fine delay: Current
DIMM 4 Clock fine delay: Current
Ch 2 Command fine delay: Current
Ch 2 Control fine delay: Current
Ch1Ch2 CommonClock Setting: Auto
Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto
Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto
CAS Latency Time (tCL): AUTO
RAS# to CAS# Delay (tRCD): AUTO
RAS# Precharge (tRP): AUTO
Precharge Delay (tRAS): AUTO
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO
Read delay phase adjust: Enter
Ch1 Read delay phase (4~0) 7-7-7-7-6
Channel 1 Phase 0 Pull-In: Auto
Channel 1 Phase 1 Pull-In: Auto
Channel 1 Phase 2 Pull-In: Auto
Channel 1 Phase 3 Pull-In: Auto
Channel 1 Phase 4 Pull-In: Auto
Ch2 Read delay phase (4~0) 0-0-0-0-0
Channel 2 Phase 0 Pull-In: Auto
Channel 2 Phase 1 Pull-In: Auto
Channel 2 Phase 2 Pull-In: Auto
Channel 2 Phase 3 Pull-In: Auto
Channel 2 Phase 4 Pull-In: Auto
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO