DFI UT X48-T3RS LanParty - Living Review

[Clunk]

Hmmm, that's interesting.

Has anyone got 500x9.5 or 500x9 and 2000Mhz RAM stable yet?

Anyone got significantly over 500FSB with a higher multi - regardless of the RAM speed?

[supershanks]

3,920Mhz 490x8@400/1600= 1,960Mhz 7-7-7-22
Managed to get to 490 but still no joy on >=500

Click to Enlarge
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Bios X48BD620

CPU Feature
Thermal Management Control:.......... Enabled
PPM(EIST) Mode:........................... Disabled
Limit CPUID MaxVal:.........................Disabled
CIE Function: ................................Disabled
Execute Disable Bit:........................ Disabled
Virtualization Technology:................ Disabled
Core Multi-Processing:.................... Enabled

Exist Setup Shutdown:................... Mode 2
Shutdown after AC Loss:................ Disabled
O.C. Fail Retry Counter:..................0 
CPU Clock Ratio.............................:8
CPU N/2 Ratioo.............................: Disabled
Target CPU Clock..........................: 3,920Mhz.
CPU Clock....................................: 490
Boot Up Clock...............................: Auto
CPU Clock Amplitude......................: 700mV
CPU Clock0 Skew........................... 0ps:
CPU Clock0 Skew........................... 0ps
DRAM Speed.................................: 400/1600
Target DRAM Speed........................: 1,960
PCIE Clock....................................: 104mhz
PCIE Slot Config.............................: 1X 1X

CPU Spread Spectrum......................: Disabled
PCIE Spread Spectrum:.................... Disabled
SATA Spread Spectrum....................: Disabled

Voltage Settings
CPU VID Control..............................: 1.38125v
CPU VID Special Add Limit.................: Enabled
CPU VID Special .............................: Auto
DRAM Voltage Control......................: 2.05v
SB Core/CPU PLL Voltage..................: 1.640v
NB Core Voltage..............................: 1.566v
CPU VTT Voltage.............................: 1.290v
Vcore Droop Control.........................: Enabled
Clockgen Voltage Contro...................l: 3.45v
GTL+ Buffers Strength......................: Strong
Host Slew Rate...............................: Weak
GTL REF Voltage Control...................: Disable
x CPU GTL1/3 REF Volt......................: 113
x CPU GTL 0/2 REF Volt.....................: 100
x North Bridge GTL REF Volt................: 110

DRAM Timing Page
Enhance Data Transmitting.................Auto
Enhance Addressing........................Auto
T2 Dispatch...............................Auto
CAS Latency Time (tCL)....................7
RAS# to CAS# Delay (tRCD)...............7
RAS# Precharge (tRP).......................7
Precharge Delay (tRAS)....................22
All Precharge to Act...........................8
REF to ACT Delay (tRFC)...................60
Performance Level.............................7
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)....................22
Rank Write to Read (tWTR).................17
ACT to ACT Delay (tRRD)...................4
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP).................6
ALL PRE to Refresh...............................8

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Enabled
Channel 1 Phase 1 Pull-In.................Enabled
Channel 1 Phase 2 Pull-In.................Enabled
Channel 1 Phase 3 Pull-In.................Enabled
Channel 1 Phase 4 Pull-In.................Enabled

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
Ch1 DLL Default Skew Model...................Model 3
Ch2 DLL Default Skew Model...................Model 3

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 489ps
DIMM 2 Clock fine delay...................Current 489ps
DIMM 1 Control fine delay.................Current 434ps
DIMM 2 Control fine delay.................Current 473ps
Ch 1 Command fine delay...................Current 560ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 686ps
DIMM 4 Clock fine delay...................Current 686ps
DIMM 3 Control fine delay.................Current 607ps
DIMM 4 Control fine delay.................Current 654ps
Ch 2 Command fine delay...................Current 693ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

Common CMD to CS Timing...................2N

[Praz]

Still tuning GTLREF to get the board voltages in check. Overall settings appear to be close though.

[carnage]

hi need help with my proc getting my board to be stable at 3.6

right now im having problem being able to boot on 3.5

here's my settings. and im using a Q9450

cpu vid control 1.35
cpu vid special add limit enabled
cpu vid speciad add auto
dram voltage control 1.855
sb core/cpu pll voltagae 1.510
nb core voltage 1.405
cpu vtt voltage 1.144
vcore droop control enabled
clockgen voltage control 3.45
gtl+ buffers strength strong
host slew rate weak
gtl ref voltage control disabale

[Kelainefes]

Probably you won't be able to get your system stable at much over 3.4 GHz with a Q9450 it seems that that processor hits a wall around that frequency.
Or so i hear from the guys who own it.

[supershanks]

Following on from Praz's discovery

tRD - 8.5, Memset Misreads The Value When Set Manually

I've found 2 more. These also occur when values are set manually in bios.
Working at 485 400/1600 on Auto
Write to Precharge Delayed (tWR) = 20
Write to read Delayed (tWTR) = 16
I manually changed to:-
Write to Precharge Delayed (tWR) = 22
Write to read Delayed (tWTR) = 17
with the resulting memset values :-
Write to Precharge Delayed (tWR) = 26 (+4)
Write to read Delayed (tWTR) = 21 (+4)

Memset Version 3.5

[Praz]

Some of the straps, tRTP is also displayed wrong in MemSet.

[supershanks]

Some of the straps, tRTP is also displayed wrong in MemSet.

Thanks for that Praz , not moved that far from 400 strap

[Glennswe]

I also got this lovely DFI board and sold out my terrible Striker 2 Extreme and I must say this is heaven. I love to overclock and adjust things but have almost always had Asusboards (about 150, i'm an old fart hehe). It was very confusing from the start with all the options in bios but, I try to follow Clunk, Praz.Supershanks and all other guys that are working very hard with this board and what they are testing. I just want to say thanks for all your hard work, keep it up I might aswell post a phot of my rig, hope it's ok.

[Praz]

Been working with the 06/27 BIOS the last few days that's posted at the DFI website. Got some stable settings together and will try to get them posted in the next few days. Check out the memory bandwidth using 2x1GB OCZ 1600EB sticks.