Overclocking Q9450 settings/results

[CrapCrasher]

Hi, this is my first attempt with DFI, after reading forum's I started my OC attempt, this are my settings OC at 3400mhz (8x425), which seems decent stable.

CPU 1.35000v
DRAM 2.03v
SB 1.510v
NB 1.392v
VTT 1.250v

GTL enabled at 115-107-100

My goal is reach 3600mhz (8x450) stable, atm i wasn't even able to pass the bios load at this speed, anyone can share or help me out with this?

[tozas1979]

Hi,

I think Clunk would say something like this:

Originally Posted by Clunk

Welcome to the forums

Can you grab the BIOS template from the Intel overclocking section sticky and list all your settings please

I´m overclocking my system with an Q9450@3.4Ghz, shows us your config for a better understanding. And in your signature shows your config for a better help

[CrapCrasher]

My BIOS settings are exactly those from the DFI LT X48-T2R template as I used it as start point, the only changes are those I listed in my previous post. (signature is edited)

[Clunk]

Welcome to the forums Mr Crasher

Tozas is right, that's what I'm going to say, it just helps us to see all your settings in one place and saves us going finding the template that you mean (I still don't know which one it is )

[CrapCrasher]

Ok here is my Template, I hope this make it easier for you all

Genie BIOS Template.

[code]
CPU Feature
Thermal Management Control: Disabled
PPM(EIST) Mode: Disabled
Limit CPUID MaxVal: Disabled
CIE Function: Disabled
Execute Disable Bit: Disabled
Virtualization Technology: Disabled
Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8X
Target CPU Clock: 3400
CPU Clock: 425
Boot Up Clock: AUTO
DRAM Speed: 800
Target DRAM Speed: 1021
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.35000v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.03v
SB Core/CPU PLL Voltage: 1.510v
NB Core Voltage: 1.392v
CPU VTT Voltage: 1.250v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Enable
x CPU GTL1/3 REF Volt: 115
x CPU GTL 0/2 REF Volt: 107
x North Bridge GTL REF Volt: 100

DRAM Timing
Enhance Data transmitting: AUTO
Enhance Addressing: AUTO
T2 Dispatch: Disabled

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
DIMM 1 Clock fine delay: Current
DIMM 2 Clock fine delay: Current
Ch 1 Command fine delay: Current
Ch 1 Control fine delay: Current


Ch2 Clock Crossing Setting: AUTO
DIMM 3 Clock fine delay: Current
DIMM 4 Clock fine delay: Current
Ch 2 Command fine delay: Current
Ch 2 Control fine delay: Current

Ch1Ch2 CommonClock Setting: Auto

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 15
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
Channel 1 Phase 0 Pull-In: Auto
Channel 1 Phase 1 Pull-In: Auto
Channel 1 Phase 2 Pull-In: Auto
Channel 1 Phase 3 Pull-In: Auto
Channel 1 Phase 4 Pull-In: Auto

Ch2 Read delay phase (4~0)
Channel 2 Phase 0 Pull-In: Auto
Channel 2 Phase 1 Pull-In: Auto
Channel 2 Phase 2 Pull-In: Auto
Channel 2 Phase 3 Pull-In: Auto
Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

[Clunk]

You seem to be doing a good enough job so far without our help

Looking at other peoples results with the Q9450, 425x8 seems to be a sticking point.

You can try extra VTT and extra NB voltage, and also a touch more vcore.

Keep in mind though that you will need to readjust your GTL REF voltages if you change your VTT. Just use the same method/table that you used to get stable for 425x8 and adjust accordingly

[CrapCrasher]

After some further tweaking I was able to lower some settings, but maintaining a perfect stability, my next goal is to reach same stability at 3600mhz which looks some more complicated apparently to achive, anyway I wanna share my latest settings which work stable at 3400mhz.

[code]
CPU Feature
Thermal Management Control: Disabled
PPM(EIST) Mode: Disabled
Limit CPUID MaxVal: Disabled
CIE Function: Disabled
Execute Disable Bit: Disabled
Virtualization Technology: Disabled
Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8X
Target CPU Clock: 3400
CPU Clock: 425
Boot Up Clock: AUTO
DRAM Speed: AUTO
Target DRAM Speed: 1021
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.33750v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.03v
SB Core/CPU PLL Voltage: 1.510v
NB Core Voltage: 1.367v
CPU VTT Voltage: 1.250v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Enable
x CPU GTL1/3 REF Volt: 115
x CPU GTL 0/2 REF Volt: 107
x North Bridge GTL REF Volt: 100

DRAM Timing
Enhance Data transmitting: AUTO
Enhance Addressing: AUTO
T2 Dispatch: Disabled

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
DIMM 1 Clock fine delay: Current
DIMM 2 Clock fine delay: Current
Ch 1 Command fine delay: Current
Ch 1 Control fine delay: Current


Ch2 Clock Crossing Setting: AUTO
DIMM 3 Clock fine delay: Current
DIMM 4 Clock fine delay: Current
Ch 2 Command fine delay: Current
Ch 2 Control fine delay: Current

Ch1Ch2 CommonClock Setting: Auto

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 15
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
Channel 1 Phase 0 Pull-In: Auto
Channel 1 Phase 1 Pull-In: Auto
Channel 1 Phase 2 Pull-In: Auto
Channel 1 Phase 3 Pull-In: Auto
Channel 1 Phase 4 Pull-In: Auto

Ch2 Read delay phase (4~0)
Channel 2 Phase 0 Pull-In: Auto
Channel 2 Phase 1 Pull-In: Auto
Channel 2 Phase 2 Pull-In: Auto
Channel 2 Phase 3 Pull-In: Auto
Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

[Clunk]

Thanks for sharing the settings

[fowler003]

wish I'd seen this last week, would have saved me a lot of faffing about. I've got the settings for 3.4Ghz running prime95(blend test) at the moment, its been over 6hrs so looks like its going to be stable(I've found that if its going to fail it seems to be in the first 6hrs).

any luck with 3.5ghz+? I'm going to be having a play around to see if I can, from what I've read its need quite a bit of voltages to get stable.

[CrapCrasher]

Originally Posted by fowler003

wish I'd seen this last week, would have saved me a lot of faffing about. I've got the settings for 3.4Ghz running prime95(blend test) at the moment, its been over 6hrs so looks like its going to be stable(I've found that if its going to fail it seems to be in the first 6hrs).

any luck with 3.5ghz+? I'm going to be having a play around to see if I can, from what I've read its need quite a bit of voltages to get stable.

I tryed at 3600mhz, but I seen soon enough that it's a hell of work to get it, so actually I am working on a 3552ghz config (8x444mhz) which seems some easier to reach but I haven't found any enough stable settings atm, the secret is again the GTL mainly, but had not enough luck yet, I cannot stay stable more than 6-7min of prime95 test; unfortunately I will have to take a pause soon from it as I will be offline next week, but as soon I am back the week after I will get back on testing further and if I find a stable configuration I will post it here again.

Of course I invite anyone else to post his results if anybody was able to fix stable settings at 3.5+ or 3.6ghz, would be even a nice idea to build some public DB archive with achivied results with proper bios settings of members of this forum if Clunk like the idea